1. Field of Invention
This invention relates to a semiconductor wafer package. More particularly, the present invention is related to a semiconductor wafer package having a plurality of solder bumps encompassed by a plurality of bump-reinforced collars respectively and the manufacturing method thereof.
2. Related Art
In this information explosion age, integrated circuits products are used almost everywhere in our daily life. As fabricating technique continue to improve, electronic products having powerful fictions, personalized performance and a higher degree of complexity are produced. Nowadays, most electronic products are relatively light and have a compact body. Hence, in semiconductor production, various types of high-density semiconductor packages, for example ball grid array package (BGA), chip-scale package (CSP), multi-chips module package (MCM) and flip chip package (F/C), have been developed.
However, as mentioned above, flip chip is one of the most commonly used techniques for forming an integrated circuits package. Compared with a wire-bonding package or a tape automated bonding (TAB) package, a flip-chip package has a shorter electrical path on average and has a better overall electrical performance. In said flip-chip package, the bonding pads on a chip and the contacts on a substrate are connected together through a plurality of bumps formed by the method of bumping process. It should be noted that there is further an under bump metallurgy layer disposed on the bonding pads of the chip to be regarded as a connection medium for connecting to the bumps and enhancing the mechanical strength of the connection of the chip to the substrate after said chip is attached to the substrate.
Moreover, said manufacturing method of a semiconductor wafer package is usually utilized in flip chip technology. Therein, a plurality of under bump metallurgy layers are formed on the corresponding bonding pads of the wafer respectively, and a plurality of solder balls or bumps are mounted onto the under bump metallurgy layers so as to be regarded as interconnections for electrically and mechanically connecting the chip and the substrate when the chip is flip-chip bonded to the substrate.
Referring to FIG. 1, it illustrates a partially cross-sectional view of a conventional semiconductor wafer 100. Therein, the semiconductor wafer 100 has a plurality of bonding pads 102 and a passivation layer 104 exposing the bonding pads 102. Moreover, under bump metallurgy layers 106 are formed on the bonding pads 102 respectively. After a semiconductor wafer 100 as shown above is provided, a plurality of reinforced layers 108 are formed on the under bump metallurgy layers 106, preferably, said reinforced layers 108 are located over the bonding pads 102. Afterwards, a plurality of solder bumps or solder balls 109 are disposed on the reinforced layers 108. Generally speaking, the reinforced layers are made of a material comprising polyimide, Benzocyclobutene (BCB) and polymer materials.
Next, referring to FIG. 1 again and FIG. 2, when the solder bumps 109 are performed a reflow process, the reflowed solder bumps 110 are securely attached to the under bump metallurgy layers 106 and said reinforced layers 108 are melted to be transformed into a plurality of bump-reinforced collars 112 to cover the periphery of each solder bumps 110 as shown in FIG. 2.
In general, each of the under bump metallurgy layers 106 mainly comprises an adhesive layer, a barrier layer and a wetting layer. The adhesive layer is utilized to enhance the mechanical strength of the connection of the bonding pad 102 to the barrier layer, wherein the material of the adhesive layer is made of aluminum or titanium. The barrier layer is utilized to avoid the diffusion of the underlying metal, wherein the material of the barrier layer usually includes nickel-vanadium alloy, nickel-copper alloy and nickel. In addition, the wetting layer, for example a copper layer, is utilized to enhance the wettability of the solder bump 109 with the under bump metallurgy layer 106. It should be noted that the under bump metallurgy layers 106 are formed through the processes of placing photo-resist, proceeding plating or sputtering metal on the surface of the semiconductor wafer 100 and etching the metal.
As mentioned above, there is needed the bump-reinforced collar 112 with a thickness not less than first-six of the diameter or the height of the reflowed solder bump 110 to well cover the reflowed solder bump 110 and enhance the mechanical reliability of the reflowed solder bump 110. To be noted, each of the reinforced layers 108 is disposed on the corresponding bonding pad 102 through printing process by using photo-mask and stencil, accordingly, said reinforced layer 108 is not well and equally distributed on the under bump metallurgy layer 106. Moreover, the solder bumps 109 are directly placed on the reinforced layers 108 before the bumps 109 are reflowed; and then the reinforced layers 108 are melted to be transformed into bump-reinforced collars 112 to partially cover and encompass the reflowed solder bumps 110 to have the reflowed solder bumps 110 securely attached to the under bump metallurgy layers 106 by penetrating the reinforced layers 108 after reflowing the solder bumps 110. Thus, the portion of each of the reflowed solder bumps 110 not covered by the bump-reinforced collar 112—is not substantially the same with each other. Namely, the height of each reflowed solder bump 110 encompassed by the reinforced collar 112 is not substantially the same with each other, for example H1 is different from H2 as shown in FIG. 2.
Per the above disadvantages, it will lower the mechanical reliability of the semiconductor wafer package and the combination of said chip of the semiconductor wafer package and substrate. Therefore, providing another method for forming bumps to solve the mentioned-above disadvantages is the most important task in this invention.